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Conference paper

Low Voltage, High Power Electronic Load Design for FPGA Current Draw Reproducing

S. Przybył, P. Sarna, Z. Kulesza, M. Zubert (Lodz Univ. of Techn., Poland)

FPGA devices are complex entities which can draw extremely high currents from low voltage rails. This presents multiple problems during the design of power supplies for FPGA circuits. In this paper, an electronic load capable of replicating the current draw from FPGA circuits will be introduced, which will streamline the design of low-voltage, high-power supplies and enable robust testing of designed electrical power rails. Designing electronic loads is a complex procedure, it requires careful design of the schematic, special considerations for the layout to keep the resistance within budget, and additional thermal considerations must also be taken into account.

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Receipt of papers:

March 15th, 2025

Notification of acceptance:

April 30th, 2025

Registration opening:

May 2nd, 2025

Final paper versions:

May 15th, 2025