Fractional Spurious Tones Analysis of the Space-Time Averaging PLL

R. Wiliński, P. Gryboś (AGH Univ. of Krakow, Poland)

This article presents a step-by-step process for modeling and analyzing the Space-Time Averaging Phase-Locked Loop architecture, which enables fractional frequency synthesis while significantly reducing the quantization error caused by fractional division. This reduction is achieved through the use of spatial averaging implemented as array of dividers, phase-frequency detectors, and charge pumps. A tree-structured, switching-block-based digital encoder is employed to generate the control signals for the dividers. The critical part of the design from the loop dynamics point of view is implemented at the transistor level using TSMC 40nm CMOS technology, while the reminder is modeled in the Verilog-A Hardware Description Language. The analysis focuses primarily on the fractional spurious tones originating from the quantization error. The Discrete Fourier Transform is used to obtain the output frequency spectra of the space-time and time averaging PLL to evaluate the effectiveness of spatial averaging in reducing quantization noise.