A Thermal Behavior of Lateral (VESTIC) BJTs on SOI Substrate

P. Mierzwiński (Warsaw Univ. of Techn., Poland)

This paper analyzes the thermal behavior of lateral (Vertical Slit Transistor Integrated Circuits, VESTIC) and vertical BJTs on SOI substrates, focusing on self-heating effects, heat dissipation mechanisms, and thermal stability. The buried oxide (BOX) layer in SOI significantly impacts heat flow, leading to localized hot spots in vertical BJTs and more distributed heating in lateral BJTs. Using numerical simulations and experimental data, we evaluate thermal management strategies and their implications for complementary bipolar logic (CBip). The findings highlight the need for optimized device layouts and biasing techniques to mitigate self-heating, ensuring stable and efficient operation of SOI-based bipolar circuits.