Implementation of a PLL Loop Circuit for Frequency Synthesis in 65 nm CMOS Technology

M. Tymińska (Warsaw Univ. of Techn., Poland), M. Kucharski (OmniChip Sp. z o.o., Poland), W. Pleskacz (Warsaw Univ. of Techn., Poland)

This paper presents the design and implementation of a phase-locked loop (PLL) circuit in 65 nm CMOS technology, dedicated to frequency synthesis and multiplication in radio frequency (RF) applications. The circuit processes an input signal of 13.56 MHz and generates a multiplied output signal of 867.84 MHz in the ultra high frequency (UHF) band, making it suitable for short-range communication systems such as radio-frequency identification (RFID) and near-field communication (NFC). The circuit was designed to ensure low phase noise, frequency stability, and fast locking time. The results demonstrate the feasibility of the proposed PLL architecture for modern wireless communication systems, highlighting its potential for integration into advanced RF applications.