Toggle accesibility mode

Conference paper

Design Considerations for Integrated SiGe BiCMOS Phase-Locked Loops in the Millimeter-Wave Band

F. Herzel, A. Ergintav, C. Carta, G. Fischer (IHP Frankfurt (Oder), Germany)

We present design guidelines for analog phase-locked loops (PLL) at millimeter wave (mmWave) frequencies in SiGe BiCMOS technology. Emphasis is placed on a robust functionality with a relatively constant phase noise performance under ionizing radiation in space. The analog tuning range of the voltage-controlled oscillator (VCO) is split into coarse and fine tuning. Using negative feedback in the fine tuning loop of the PLL, the fine tuning control voltage is kept close to the VCO gain maximum for a constant PLL loop bandwidth. Together with self-triggered sub-band switching, a long lifetime of the PLL is expected, since any VCO degradation will be compensated keeping VCO gain and loop bandwidth fairly constant. An integrated SiGe-HBT based phase detector is proposed, which allows mmWave phased-array transceivers to be driven by a low-jitter frequency source in the lower GHz range.

Download one page abstract

Receipt of papers:

March 15th, 2025

Notification of acceptance:

April 30th, 2025

Registration opening:

May 2nd, 2025

Final paper versions:

May 15th, 2025