Design of the Charge-Sampling Multiplying PLL in CMOS 40 nm

J. Zając, P. Kmon (AGH Univ. of Krakow, Poland)

This paper presents the design of the low power Charge Sampling Phase-Locked Loop working on 11 GHz. The presented PLL works with the 100MHz reference source and its main advantage is a phase detector working in charge domain allowing to minimize power consumption and simultaneously keeping the high gain of the phase difference. To alleviate spur transfer from periodic phase detector to PLL output high DM/CM OTA amplifier is used with CM amplifier, that adjusts its output level improving frequency range. Also, the differential input class D/F2 VCO with one turning inductor is used. The proposed PLL is designed in 40nm process, works with two supply sources 1.1V and 0.6V and consumes about 5mW of power.