Conference paper

Automatic Design of a Cascoded-Inverter-Based Charge-Sensitive Amplifier Using gm/ID Technique and Particle Swarm Optimization in 28 nm CMOS

P. Kaczmarczyk (AGH Univ. of Science and Techn. in Krakow, Poland)

In this paper, an automated design procedure of a cascoded-inverter-based charge-sensitive amplifier (CSA) using the gm/ID method and particle swarm optimization (PSO) is presented. Assuming certain fixed values, such as transistors' length, supply voltage, feedback resistance, and input, output and feedback capacitances, the algorithm is able to find the proper transistors' width and cascode biasing voltages, to meet specified requirements, such as power consumption, gain, bandwidth, input/output DC level and input-referred noise. A CSA designed in 28 nm CMOS technology using the presented method achieves 500 V/V gain, 3.7 MHz bandwidth and 71 e- ENC, consuming 2.2 uW of power from a 1.1 V supply.

Download one page abstract

Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024