On-chip Infrastructure for Mission-mode Monitoring of Aero-space Applications: Towards Silicon Lifecycle Management


Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced integrated circuit (IC) and electronics since the sixties. Nevertheless, it is well recognized that such scaling has introduced new (and major) reliability challenges to the semiconductor industry.

This talk summarizes the on-chip infrastructure such as sensors and dedicated HW redundancy under development at IHP Microelectronics. This infrastructure deals with, for instance, detecting single-event upset (SEU) in memory elements and single-event transient (SET) in logic, measuring electronics aging and tracking in-field real-time circuit speed performance degradation during IC lifetime. Furthermore, after manufacturing process, on-chip sensors can also be used to assess silicon for device screening. Ultimately, this infrastructure allows predicting in-flight SEU rate and remaining IC life-span. Dedicated on-chip watchdogs to guarantee mixed-criticality task execution in real-time operating system (RTOS) is further introduced. Embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std.

Currently, this on-chip infrastructure is being implemented by IHP in different versions of a RISC-V processor. Such design is based on a CMOS 130nm rad-hard technology also developed at IHP. An FPGA-mapped demonstrator of one of the developed RISC-V processors and experimental results will be briefly presented.


On-chip infrastructure, in-field monitoring, cross-layer resilience, on-chip analytics, in-flight error rate and IC life-span predictions.


15 + 60 minutes.


Free of charge


Fabian Luis Vargas

Senior Scientist – Project Leader

IHP – Leibniz Institute for High Performance Microelectronics, Germany


Short Bio:

Fabian Vargas obtained the Ph.D. Degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG), France, in 1995. At present, he is Senior Scientist at IHP - Leibniz Institute for High Performance Microelectronics, Germany, where he works on the design of on-chip sensors and cross-layer resilience for aerospace systems.

Vargas has served as Technical Committee Member and Guest-Editor in many IEEE-sponsored conferences and journals. He holds several patents and published over 200 refereed papers. Vargas was researcher of the BR National Science Foundation from 1996 to 2023.

He co-founded the IEEE-Computer Society Latin American Test Technology Technical Council (IEEE LA-TTTC) in 1997 and the IEEE Latin American Test Symposium (LATS) in 2000. He received the Meritorious Service Award of the IEEE Computer Society for providing significant services as chair of these groups. Vargas is Golden Core Member of the IEEE Computer Society and Senior Member of the IEEE.


Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024