MIXDES - The MIXDES 2002 information

9th International Conference
Mixed Design of Integrated Circuits and Systems
Wrocław, 20-22 June 2002

The MIXDES 2002 Conference took place in Wrocław, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Interdisciplinary Applications
  9. Education

The total number of 136 papers from 27 countries were accepted for publication including 6 invited papers.

The following invited papers were presented during the conference:

  1. Analytical SOI MOSFET Model Valid for Graded-channel Devices, B. Iniguez (Univ. Rovira i Virgili, SPAIN), M.A. Pavanello (State Univ. Campinas and Escola Politecnica da Univ. de Sao Paulo, BRAZIL), J.A. Martino (Escola Politecnica da Univ. de Sao Paulo, BRAZIL), D. Flandre (Univ. Catholique de Louvain, BELGIUM)
  2. CMOS Design of Cellular Mixed-Signal Vision Chips, A. Rodriguez-Vazquez, R. Dominguez-Castro, S. Espejo, R. Carmona, G. Linan (Instituto de Microelectronica de Sevilla, SPAIN)
  3. Deep Submicron CMOS Scalling Challenges, G. Badenes, M. Jurczak (IMEC, BELGIUM)
  4. Mixed-signal Multi-level Circuit Simulation: An Implict Mixed-mode Solution, X. Zhou (Nanyang Technological Univ., SINGAPORE)
  5. Optimal/Robust Design of Nonlinear Multi-physics Systems - MOEMS & Biochips Examples, M.J. Saran (OES and CWRU, USA)
  6. Recent Advances and Future Trends in RF Power FET Technologies, K. Shenai (Univ. Illinois, USA)

The following special sessions were organised during the conference:

  1. MOS-AK Group Session I
    • Advanced Calibration Techniques for On-wafer Microwave Measurements and Characterisation, A. Lord (Cascade Microtech Europe Ltd., UK)
    • Compact Device Modeling Using VerilogA and ADMS, L. Lemaitre (MOTOROLA Geneva, SWITZERLAND), C. McAndrews (MOTOROLA Phoenix, USA), W. Grabinski (MOTOROLA Geneva, SWITZERLAND)
    • EKV 3.0: An Analog Design-oriented MOS Transistor Model, M. Bucher (National Techn. Univ. Athens, Greece and Smart Silicon Systems S.A., SWITZERLAND), J.-M. Sallese, F. Krummenacher (Swiss Federal Inst. of Techn., SWITZERLAND), D. Kazazis (National Techn. Univ. Athens, GREECE), C. Lallement (ERM-PHASE, ENSPS, FRANCE), W. Grabinski (MOTOROLA Geneva, SWITZERLAND), C. Enz (MOTOROLA Geneva and Swiss Center for Electronics and Microtechniques, SWITZERLAND)
    • gm/Id-Based MOSFET Modeling and Modern Analog Design, D. Foty (Gilgamesh Associates, USA), D. Binkley (Univ. North Carolina/Charlotte, USA), M. Bucher (National Techn. Univ. Athens, GREECE)
    • High Level Description of Thermodynamical Effects in the EKV 2.6 MOST Model, C. Lallement, F. Pecheux (ERM-PHASE, ENSPS, FRANCE), W. Grabinski (MOTOROLA Geneva, SWITZERLAND)
    • Large-signal Network Analyzer Measurements and Their Use in Device Modelling, E.P. Vandamme (Agilent Technologies, BELGIUM), W. Grabinski (MOTOROLA Geneva, SWITZERLAND), D. Schreurs (Katholieke Univ. Leuven, BELGIUM)
    • Multi-level Modeling of Deep-submicron MOSFETs and ULSI Circuits, X. Zhou (Nanyang Technological Univ., SINGAPORE)
  2. MOS-AK Group Session II
    • Applications of LTCC Ceramics in Microwave, L.J. Golonka (Wroclaw Univ. of Techn., POLAND), H. Thust (Ilmenau Tech. Univ., GERMANY)
    • A Unified Environment for Modeling Very Deep Submicron MOS Transistors inside Agilent's IC-CAP, T. Gneiting (Advanced Modeling Solutions, GERMANY), H. Khakzar (Univ. of Applied Science Esslingen, GERMANY)
    • Consistent DC and AC Models of Non-fully Depleted SOI MOSFETs in Strong Inversion, D. Tomaszewski (Institute of Electron Techn., POLAND), L. Lukasiak (Warsaw Univ. of Techn., POLAND), K. Domanski (Institute of Electron Techn. and Warsaw Univ. of Techn., POLAND), A. Jakubowski (Warsaw Univ. of Techn., POLAND), K. Kucharski (Institute of Electron Techn., POLAND), J. Gibki (Warsaw Univ. of Techn., POLAND)
    • From Continuous Field Modeling to MEMS Macromodels, G. Wachutka (Munich Univ. of Techn., GERMANY)
    • MOS Transistor Modeling for HV Processes, E. Seebacher, G. Rappitsch, H. Holler (austriamicrosystems AG, AUSTRIA), W. Posch (Graz Univ. of Techn., AUSTRIA)
    • Multielectrode System for Imaging Neuronal Activity in Live Retinal Tissues, W. Dabrowski (Univ. of Mining and Metallurgy, POLAND)
    • Principles of the 1-T DRAM Concept on SOI, J.-M. Sallese, S. Okhonin (Swiss Federal Inst. of Techn., SWITZERLAND), P. Fazan (Swiss Federal Inst. of Techn. and Innovative Silicon Solutions, SWITZERLAND), M. Nagoga (Swiss Federal Inst. of Techn., SWITZERLAND)
  3. Special Session on REASON
    • Application Specific Integrated Circuits for Local Industries: The Polish Experience, A. Kobus, T. Janiszewki (Institute of Electron Techn., POLAND), W. Pleskacz, W. Kuzmicz (Warsaw Univ. of Techn., POLAND)
    • How to Raise Schoolchildren's Interest to Microelectronics Studies, M. Blyzniuk, I. Kazymyra (Lviv Polytechnic National Univ., UKRAINE)
    • Microelectronics: Manufacturing, Design, Education and the REASON Project, W. Kuzmicz (Warsaw Univ. of Techn., POLAND)
    • Research and Training of RF Analog and Wireless Systems Design at Vladimir University, and Actions for REASON Project, V.N. Lantsov, A. Merkutov, M. Morozov, S.G. Mosin (Vladimir State Univ., RUSSIA)
    • The EUROPRACTICE IC Service Extends Its Portfolio of CAD Tools and Prototyping Services to Silicon RF and System Level Integration, C. Das (IMEC, BELGIUM), J. McLean (CLRC, UK)
  4. Special Session on SEWING
    • Automatic Stand for IS-FET Sensors Parameters Identification, R. Jachowicz, J. Weremczuk, J. Sochon (Warsaw Univ. of Techn., POLAND)
    • Blind Source Separation in an Array of ISFET Sensors: II. Simulations, G. Bedoya, S. Bermejo (Tech. Univ. Catalunya, SPAIN)
    • Blind Source Separation in an Array of ISFET Sensors: I. Mathematical Foundations, S. Bermejo (Tech. Univ. Catalunya, SPAIN)
    • Building Web Services Using J2EE Platform for SEWING Project, B. Sakowicz, R. Brzozka, M. Dzieniecki, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • CHEMFET Sensors Modeling for Water Monitoring Systems Design, J. Ogrodzki (Warsaw Univ. of Techn., POLAND)
    • Comparison of Two Methods of A/D Processing on a Chosen Examples Dedicated for Silicon Microsystem of Water Pollution Monitoring, M. Szermer, M. Daniel, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • IDS Application: Integrated Dispatching System with Telephone, Fax and E-mail Features, M. Wodzislawski, K. Szaniawski, M. Orlikowski, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Ion-selective Sensors Modelling for CAD, M. Daniel, M. Szermer, A. Napieralski (Tech. Univ. Lodz, POLAND), W. Wroblewski, A. Dybko (Warsaw Univ. of Techn., POLAND)
    • Looking at Processors for the SEWING Smart Sensor, V. Parisi i Baradad, S. Bermejo, J. Cabestany (Tech. Univ. Catalunya, SPAIN)
    • Natural Water Analysis Based on Multisensor System, M. Chudy, W. Wroblewski, A. Dybko, Z. Brzozka (Warsaw Univ. of Techn., POLAND)
    • On Dependence of CHEMFET Sensor Response on Operating Point, L. Opalski, Z. Gniewinski, W. Wroblewski (Warsaw Univ. of Techn., POLAND)
    • SEWING Data Transmission Through Mobile Phones, A. Goralski (Warsaw Univ. of Techn., POLAND)
    • Study of CHEMFET Interface Electronics, K. Tukkiniemi (VTT, FINLAND)
    • Technology and Measurements of Backside Contacted ISFETs, B. Jaroszewicz, P. Grabiec, J. Koszur, A. Kociubinski, Z. Brzozka (Institute of Electron Techn., POLAND)
    • Water Tunnel and Laser Doppler Anemometry in Underwater Monitoring Applications. EU SEWING Project, O. Leon, G. De Mey, E. Dick (Univ. Ghent, BELGIUM)

The following papers has been awarded:

  • IEEE EDS Polish Chapter Award was presented to:
    • Novel High Performance CMOS Current Conveyor, B. Calvo, S. Celma, P.A. Martinez, M.T. Sanz (Univ. Zaragoza, SPAIN)
  • Outstanding Paper Award was presented to:
    • Application of IEEE1394 Interface for Sending Data from Infrared Camera, D. Makowski, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • A Robust Three-state PFD Architecture without Output Polarity Reversal, F. Centurelli, R. Luzzi, G. Lulli, M. Olivieri, A. Trifiletti (Univ. Rome "La Sapienza", ITALY)
    • Coupled Full-wave Optical and Semiconductor Analysis and Design of MSM Photodetectors, Z. Sikorski (CFDRC and Univ. Alabama, USA), Y. Jiang (CFDRC, USA), M. Turowski (CFDRC, USA and Tech. Univ. Lodz, POLAND), A. Przekwas (CFDRC, USA)
    • Distributed Models of Insulated Gate Bipolar Transistors for SABER Simulator, G. Bonnet, P. Austin, J.L. Sanchez (LAAS-CNRS, FRANCE)
    • Experimental CTE and Young's Modulus Determination for Electrodeposited Copper Using the Bilayer Cantilever Method, O. Perat (MOTOROLA Toulouse and LAAS-CNRS, FRANCE), E. Scheid, J.-M. Dorkel, P. Tounsi (LAAS-CNRS, FRANCE), O. Henry (MOTOROLA Toulouse, FRANCE), Y. Chung (MOTOROLA Mesa, USA), M. Zecri, J.L. Chaptal (MOTOROLA Toulouse, FRANCE)
    • Functional Decomposition as a Universal Method of Logic Synthesis for Digital Circuits, T. Luba, M. Rawski (Warsaw Univ. of Techn., POLAND), Z. Jachna (Military Academy of Techn., POLAND)
    • Hardware Implementation of Programmable Multi-layer Perceptron Structure on the Triscend System-on-Chip Devices, A. Klepaczko, A. Napieralski, R. Kielbik (Tech. Univ. Lodz, POLAND), J.M. Moreno, J. Cabestany (Tech. Univ. Catalunya, SPAIN)
    • HDL-A Description of A/D Converter Based on Delta-Sigma Modulator, A.S. Botha (Embbeded Real-Time, USA), P. Sniatala (Rochester Institute of Techn., USA)
    • Improvement of Integrated Circuit Testing Reliability by Using the Defect Based Approach, D. Kasprowicz, W. Pleskacz (Warsaw Univ. of Techn., POLAND)
    • Switched Capacitor-based Implementation of Integrate-and-Fire Neural Networks, D. Hajtas, P. Kruzlic, D. Durackova (Slovak Univ. of Techn., SLOVAKIA)
    • Transient Thermal Measurements of Integrated Circuits Based on Inverse Heating, P. Kawka (Univ. Ghent, Belgium and Tech. Univ. Lodz, POLAND), G. De Mey (Univ. Ghent, BELGIUM), A. Napieralski (Tech. Univ. Lodz, POLAND)

Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024