MIXDES - The MIXDES 2004 information

11th International Conference
Mixed Design of Integrated Circuits and Systems
Szczecin, 24-26 June 2004

The MIXDES 2004 Conference took place in Szczecin, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Embedded Systems
  9. Medical Applications
  10. Information Technology
  11. Education

The total number of 129 papers from 35 countries were accepted for publication including 6 invited papers.

The following invited papers were presented during the conference:

  1. Compact Modeling for Silicon Carbide Power Devices, H.A. Mantooth, T. McNutt (Univ. Arkansas, USA)
  2. Development of Integrated Microsensors for Chemical and Biochemical Applications, S. Baglio (Univ. Catania, ITALY)
  3. Diamond Technology for MEMS and Electronics, E. Kohn, M. Adamschik, A. Aleksov, A. Denisenko, C. Janischowsky, F. Hernandez-Guillen, A. Kaiser (Univ. Ulm, GERMANY), M. Kasu (NTT Basic Research Laboratories, JAPAN), M. Kubovic, J. Kusterer, R. Muller, P. Schmid (Univ. Ulm, GERMANY)
  4. Electronic Product Life-cycle Design-for-Test: Status and Future Challenges, B. Bennetts (Bennetts Associates, UK)
  5. Future CMOS Scaling, H. Iwai (Tokyo Inst. of Techn., JAPAN)
  6. Mixed-node Device and Circuit Simulation, S. Wagner, T. Grasser, S. Selberherr (Tech. Univ. Vienna, AUSTRIA)

The following special sessions were organised during the conference:

  1. Special Session: Advanced Compact Modeling and Its Standardization
    • A Model for Low Frequency Noise Generation in MOSFETs, A. Szewczyk (Gdansk Univ. of Techn., POLAND), J.A. Chroboczek (CEA-Grenoble, FRANCE)
    • Analytical Method for Calculating Elements of an Arbitrary Equivalent Circuit, M. Malorny, M. Schroter (Univ. of Techn. Dresden, GERMANY)
    • A New Electrothermal Model of the Power MOSFET for SPICE, J. Zarebski, K. Gorecki, D. Bisewski (Gdynia Maritime Univ., POLAND)
    • Application of the VBIC Model for SiGe:C Hetero-junction Bipolar Transistors, B. Senapati, R.F. Scholz, B. Heinemann (IHP Microelectronics, GERMANY), A. Chakravorty (IIT Kharagpur, INDIA)
    • Benchmarking of Newly-developmed Bipolar SPICE Models, S. Yoshitomi (Toshiba Semiconductor, JAPAN)
    • Benchmarking the EKV3.0 MOSFET Model in Verilog-A with 0.14µm CMOS, A. Bazigos (Nat. Techn. Univ. Athens, GREECE), M. Bucher (Tech. Univ. of Crete, GREECE), S. Yoshitomi (Toshiba Semiconductor, JAPAN)
    • Compact Modeling of Thermal Noise in the MOS Transistor, A.S. Roy (EPFL, SWITZERLAND), C.C. Enz (EPFL and CSEM, SWITZERLAND)
    • Compact Model Strategy for Studying the Impact of Intrinsic Parameter Fluctuations on Circuit Performance, B. Cheng, S. Roy, A. Asenov (Univ. Glasgow, UK)
    • Electrical Ageing Laws Included in CMOS Compact Device VHDL-AMS Model, B. Mongellaz, F. Marc, C. Bestory, Y. Danto (Univ. Bordeaux, FRANCE)
    • Modeling of 50GHz SiGe Bipolar Transistors with SGP Subcircuit Models, A.H. Pawlikiewicz (Atmel Corporation, USA)
    • MOSFET Modeling for RF-circuit Era, M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch (Hiroshima Univ., JAPAN), T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto (Semiconductor Academic Research Center, JAPAN)
    • Revised EKV Model to Apply gm/Id Methodology to Poly-Si TFT Analog Design, K. Takatori (NEC Corporation, JAPAN), D. Flandre (Univ. Catholique de Louvain, BELGIUM)
    • RF/Analog Characterisation for SiGe BiCMOS Technologies, E. Seebacher, G. Rappitsch, Z. Huszka, K. Molnar, W. Pflanzl (austriamicrosystems AG, AUSTRIA)

The following papers has been awarded:

  • Outstanding Paper Award was presented to:
    • Advanced RF Design Center - An e-Learning Course, T. Ostermann, C. Lackner, R. Koessl (Univ. Linz, AUSTRIA), R. Hagelauer (Univ. Linz and DICE GmbH & Co. KG, AUSTRIA), G. Sommer, L. Krahn, W. John (Fraunhofer Institute IZM, GERMANY), A. Arzt (Infineon Technologies AG, GERMANY), H.-P. Fuchs (DICE GmbH & Co. KG, AUSTRIA)
    • A Linear APS Cell with Frame Difference Output, F. Roewer, U. Kleine (Univ. Magdeburg, GERMANY)
    • Application of a Genetic Algorithm to Design of Radiation Tolerant Programmable Devices, D. Makowski, M. Grecki, G. Jablonski (Tech. Univ. Lodz, POLAND)
    • Application of Inverse Problem Algorithm for Estimation of Ion Mixture Composition, M. Janicki, M. Daniel, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Design of RF Sampling Receiver Front-end, K. Folkesson, D. Jakonis, J. Dabrowski, C. Svensson (Linkoping Univ., SWEDEN)
    • Design, Optimization, and Realization of SC FIR Filters Realized in CMOS 0.8µm Technology, A. Dabrowski, R. Dlugosz, P. Pawlowski (Poznan Univ. of Techn., POLAND)
    • Electronic Package Thermal Description by Dielectric Polarization Theory, P. Kawka (Tech. Univ. Lodz, Poland and Univ. of Ghent, BELGIUM), G. De Mey (Univ. Ghent, BELGIUM), A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Evaluation of Parasitic Capacitances for Interconnection Buses Crossing in Different Layers, A. Jarosz, A. Pfitzner (Warsaw Univ. of Techn., POLAND)
    • Preliminary Measurements of the Monolithic Active Pixel Detector Realized in the SOI Technology, H. Niemiec, M. Jastrzab, W. Kucewicz, S. Kuta, M. Sapor, M. Szelezniak (AGH Univ. of Science and Techn., POLAND), K. Domanski, P. Grabiec, M. Grodner, B. Jaroszewicz, A. Kociubinski, K. Kucharski, J. Marczewski, D. Tomaszewski (Institute of Electron Techn., POLAND), A. Czermak, B. Dulny, B. Sowicki, A. Zalewska (H. Niewodniczanski Inst. of Nuclear Physics, POLAND), A. Bulgheroni, M. Caccia (Univ. degli Studi dell'Insubria, ITALY)
    • Verification of TRMS with IP Component Design, K. Siekierska, A. Kokoszka, D. Obrebski, N. Lugowski (Institute of Electron Techn., POLAND), P. Fras, T. Kostienko, A. Pawlak, P. Penkala, D. Stachanczyk, M. Szlezak (Silesian Univ. of Techn., POLAND)
  • Best Poster Award was presented to:
    • Effects of Package on RF Curcuits Design, A. Szymanski, E. Kurjata-Pfitzner (Institute of Electron Techn., POLAND)


Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024