Optimisation of Ivy Bridge Topography

A. Samake, P. Kocanda, A. Kos (AGH Univ. of Science and Techn., Poland)

The article presents a quasi-optimum placement of different functional modules in an integrated circuit. The goal of quasi-optimum placement is minimization of maximum chip temperature. Firstly, a RC thermal model of the microprocessor packages is presented. Based on package’s geometry and chip floor topography the HotSpot calculates different parameters for RC thermal model. A New topography of Ivy Bridge processor was modelled using a simple heuristic approach. Therefore, its temperature profile was compared to that obtained through original published floor plan. The crated floor plan provides lower chip maximal temperature than original published one.