Applying Negative Feedback to Improve Linearity and Input Property of Analog CMOS Transresistor

R. Wojtyna (Univ. Techn. & Life Sciences, Poland)

The paper presents an idea of improving both linearity and input impedance of a simple low-voltage CMOS current to voltage converter (C-V converter). The idea is based on using negative feedback around the whole converter. Applying the proposed feedback allows us to make smaller the converter nonlinearities and reduce the converter input resistance. Necessary condition to achieve this aim is to divide the converter into two parts. The first part is a linear preamplifier and the second is a slightly nonlinear output stage. All parts are simple and the total number of CMOS transistors used to build the C-V converter is eight. Voltage signal utilized in the feedback loop is taken from the converter output stage generating the nonlinearity, is then changed into current and finally, being in the current form, goes to the C-V converter input node. In this node, external input current and the feedback current are connected in parallel. Simplicity and low supply voltage of the proposed C-V converter do not allow achieving a very good improvement of the parameters considered. In spite of that, the obtained results are satisfactory and the parameter improvement is clearly seen. Results of the presented theoretical considerations and preliminary simulations results are in a good agreement.