Distributed-Arithmetic-Based DWT Processor for Neural Recording Systems

P. Turcza (AGH Univ. of Science and Techn., Poland)

Wireless data transmission dominates the total power consumption of implanted multichannel neural recording system. However, it can be significantly reduced by using on-chip data compressor. It has been found that Discrete-time wavelet transform (DWT) is a very effective tool for compressing neural data. Therefore, in this paper a wavelet-based data compressor suitable for multichannel implanted neural recording systems is proposed. The performance of the proposed compressor operating with two different wavelete transformations is analyzed. Next, based on distributed arithmetic approach, an energy-efficient architecture for DWT processor, a central part of the compressor, is proposed. The resulting DWT processor is implemented in 180 nm AMS CMOS process. The power consumption for 32 channel four-level DWT processor amounts to about 37 µW for orthogonal DWT (symlet4) and 32 µW for biorthogonal DWT (bior3.3).