Challenges in HPC, AI for RISC-V Accelerator Chips

P. Kołodziej (Openchip, Poland)

This presentation explores the evolution of high-performance computing (HPC) architectures from traditional scalar CPU designs toward vector-oriented and heterogeneous computing models. It highlights how vector processing within the RISC V ecosystem enables scalable and efficient execution of data-parallel workloads, forming a key foundation for modern HPC and AI systems. The talk discusses the integration of vector-centric designs with accelerator-based approaches, including GPGPU-like architectures, emphasizing improvements in performance, energy efficiency, and programmability. Particular focus is placed on the benefits of open instruction set architectures, including flexibility, extensibility, and opportunities for hardware-software co-design. Openchip is realizing this concept in practice through the development of RISC V-based vector and AI accelerators within a modular, chiplet-based framework.