Analysis of the Behavior of a Memristive Device within a One-Transistor-One-Resistor Structure

N. Dersch (THM, Germany), T. Rizzi, M. Uhlmann, E. Perez-Bosch Quesada, K. Dorai Swamy Reddy, E. Perez, C. Wenger (IHP, Germany), M. Schwarz (THM, Germany), B. Iniguez (URV, Spain), A. Kloes (THM, Germany)

This paper presents an analysis of the onetransistor- one-resistor of a memristive device and an NMOS transistor. The open-source Stanford model for memristive devices is used in the circuit simulations. It is shown that two different biasing schemes are required for the SET and RESET states of the memristive devices, which changes the source reference node of the applied transistor. The steering voltage Vgs varies in the RESET state depending on the applied voltage but remains constant in the SET state. Furthermore, the effect of the transistor on the memristive device is demonstrated. A comparison of the voltage drop across an memristive device with compliance current and an MD combined with a transistor revealed significant differences. The transistor allows for the observation of phases in the voltage drop across the memristive device where the current increases but the voltage decreases. To verify this behavior, measurements were analyzed and confirmed. Finally, the influence of parasitic resistances on this phenomenon was investigated.