Conference paper

Highly Linear 4-bit Flash ADC Implemented in 22 nm FD-SOI Process

Z. Jaworski (Warsaw Univ. of Techn., Poland)

In this paper the design of 4-bit flash type analog-to-digital converter with sampling rate of 500 Ms/s has been presented. The ADC is implementation in 22 nm FD-SOI technology and use supply voltage of 0.8 V. The block is part of a sub-ranging ADC whose working principle is based on the assumption that sub-ADC and sub-DAC exhibit high linearity while they resolutions remain relatively low. In this case, linearity of the flash ADC has to be as high as in case of 8-bit converter. Thus, the most challenging task was to design comparator with resolution of +/-1.5 mV. This goal was reached owing to ability offered by the FD-SOI process to trim transistor's threshold voltage by means of modulating the back-gate polarization.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020