Conference paper

Retargeting the MIPS-II CPU Core to the RISC-V Architecture

S. Cieślak, A. Oleksiak, K. Marcinek, W. Pleskacz (Warsaw Univ. of Techn., Poland)

This paper presents the process of retargeting the existing single-issue, six stage pipeline processor core based on MIPS-II architecture to the RISC-V architecture. Both ISAs were compared and necessary code changes were implemented to the original Verilog HDL code. After retargeting, the entire processor was initially verified with functional simulation using riscv-tests and riscv-compliance suites. Moreover, performance comparison between the two ISAs was carried out using the Dhrystone and CoreMark benchmarks.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020