Conference paper

Configurable MBIST Processor for Embedded Memories Testing

A. Wojciechowski (Warsaw Univ. of Techn., Poland), K. Marcinek (Warsaw Univ. of Techn. and ChipCraft, Poland), W. Pleskacz (Warsaw Univ. of Techn., Poland)

Nowadays, demand for computing power grows faster than ever. This results in more integrated circuits are being dedicated to memories. The efficient testing of such SRAM memories is a difficult task. An integrated Memory Built-In Self-Test (MBIST) module provides an effective testing capability with reasonable area cost. This paper describes the design of a configurable MBIST processor for embedded single-port and dual-port memories testing. Embedded memory fault models were summarized. The developed test environment with memory model and fault injection capability was used to verify the effectiveness of implemented algorithms.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020