Conference paper

Substrate Coupling of DMOS Transistors in High Voltage SOI processes

K. Hirmer, K. Hofmann (Tech. Univ. Darmstadt, Germany)

Substrate coupling is an important topic for mixed-signal, RF as well as high voltage ICs. Silicon-on-insulator wafers can reduce the substrate coupling due to the buried oxide (BOX). Switching high voltage quasi-vertical double-diffused MOS transistors have their drain close to the BOX and can introduce a substrate current into the handle wafer. A substrate network as well as its extraction is presented. A fully integrated three-state inverter with up to ±300V fabricated in a 1 µm process delivers measurement results to validate the SPICE as well as 3D TCAD simulations. With the proposed method high voltage interferences on the IC can be predicted in prior to fabrication.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020