Conference paper

A Simple Ultra-low Power Opamp in 22 nm FDSOI

W. Kuźmicz (Warsaw Univ. of Techn., Poland)

An ultra-low power opamp is described. The amplifier has been designed and prototyped in 22nm CMOS FDSOI technology. Very low power consumption (below 1 μW at VDD=0.8V) and very low area (0.0277 mm2) make it suitable for multichannel bio signal recording arrays. Noise efficiency factor of 3.2 has been achieved. A unique feature of this opamp architecture is a negative feedback loop applied to the body of an input transistor, which serves as a second gate. This circuit technique, possible only in FDSOI technology, allowed to achieve perfectly linear voltage transfer curve while leaving both inputs of the amplifier free.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020