Conference paper

Decreasing Number of LUTs for Moore FSMs

A. Barkalov, L. Titarenko, K. Mielcarek (Univ. Zielona Gora, Poland), K. Krzywicki, W. Zajac (The Jacob of Paradies Univ., Poland)

A method is proposed for hardware reduction in FPGA-based Moore FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020