Conference paper

Decreasing Number of LUTs for Moore FSMs

A. Barkalov, L. Titarenko, K. Mielcarek (Univ. Zielona Gora, Poland), K. Krzywicki, W. Zajac (The Jacob of Paradies Univ., Poland)

A method is proposed for hardware reduction in FPGA-based Moore FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.

Download one page abstract

Receipt of papers:

March 1st, 2021

Notification of acceptance:

April 26th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 17th, 2021