Conference paper

High-Level Functional Test Generation for Microprocessor Modules

A. Oyeniran, R. Ubar (Tallinn Univ. of Techn., Estonia)

A new high-level implementation-independent and automated test program generation method for RISC processors is proposed. For testing the control parts of the processor modules, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the instruction group using the module under test. For generating tests for the data path of the module under test, pseudo-exhaustive patterns are used. The set of test data is generated in two parts. The first part is based on the deterministic test data generated for the control test, and the second part is formed by the sets of pseudo-exhaustive test data operands, generated for each instruction of the group separately. We investigated the feasibility of the approach and demonstrated high gate-level stuck-at-fault coverage of the generated test programs for testing the execute module of the MiniMIPS RISC processor

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Receipt of papers:

March 1st, 2021

Notification of acceptance:

April 26th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 17th, 2021