Conference paper

A Wide Band Fractional-N Synthesizer in 0.18um CMOS Process

E. Hosseini, M. Mousazadeh (Urmia Univ., Iran), A. Dadashi (Univ. Oslo, Norway)

In this paper, a wideband synthesizer with output range of 2.1GHz-2.5GHz and resolution of 1MHz and input reference of 50Mhz is proposed. In this method, firstly, by the Integer-N synthesizer based on PLL and constructed of blocks of PFD, CP, VCO and Frequency divider the input is increased with integer coefficients and it produces frequencies 2.1GHz, 2.15GHz, …, 2.5GHz very quickly. To get 1MHz steps in the output, a second loop that consists of blocks FVC, VCO and Voltage divider is used. In this method, the input frequency is high compared to the conventional methods, so the first loop will be locked very fast and the second loop will quickly move the output in steps 1MHz. As a result, changing channels will be very quick. This structure is very simple and has a low power consumption and a low output jitter. the proposed structure is designed in 0.18um CMOS process.

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Receipt of papers:

March 1st, 2021

Notification of acceptance:

April 26th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 17th, 2021