Application of Offset Trimming Circuit for Reducing the Impact of Parasitics in Capacitive Sensor Readout Circuit

P. Zajac, M. Jankowski, P. Amrozik, M. Szermer (Lodz Univ. of Techn., Poland)

After the manufacturing process of a differential capacitive MEMS sensor, a capacitance mismatch may occur, which may result in the unwanted offset in the output voltage. In this paper, we present the design of an offset trimming circuit which allows reducing this offset. The designed circuit can successfully compensate the mismatch of over 10% of the total MEMS capacitance. The novel contribution of the paper is the detailed analysis of how the offset trimming circuit can be used to mitigate the impact of parasitics. It is shown that the circuit can help reducing the voltage offset caused by parasitic capacitances due to the chip pads or those induced by the chip layout.