Conference paper

A New Very High-speed True 7-3 Compressor

S. Ghafari, M. Mousazadeh, A. Khoei (Urmia Univ., Iran), A. Dadashi (Univ. Oslo, Norway)

In this paper, a new high-speed 7-3 compressor for high-speed arithmetic operations is presented. This compressor takes advantage of the current-mode techniques, also inverter gate’s property, especially back to back inverters to achieve the minimum delay. The proposed architecture is an altered size of the input number compressor. This feature will be important when 4, 5 or 6 partial product bits exist to compress in Multiplier, which can reduce the extra area and power. All the proposed designs are evaluated by exhaustive HSPICE simulations in 0.18um standard CMOS technology with 0.18V power supply voltage and supplementary simulation have been done to examine the effect of terms. The results show performance improvements with more than 3 times higher speed and 18 percent lower PDP compared to the purely digital design.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020