Conference paper

Advanced MOS Device Technology for Low Power Logic LSI

S. Takagi, K. Kato, K. Sumita, K. Jo, C.-M. Lim, R. Takaguchi, D.-H. Ahn, J. Takeyasu, K. Toprasertpong, M. Takenaka (The Univ. of Tokyo, Japan)

MOSFETs with alternative channels such as Ge and III-Vs on the Si platform have been strongly expected over recent 15 years for high performance and low power logic devices, where the reduction in Vdd is the most critical requirement. Also, steep slope devices such as tunneling-FETs (TFETs) have stirred a strong interest from the viewpoint of ultralow power applications. In this paper, we briefly address the current status of MOSFETs and TFETs using alternative materials such as Ge, III-V and oxide semiconductors for future low power scaled devices and review the recent progress in device and process technologies on a basis of our research activities.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020