Yield and Reliability Challenges at 7nm and Below

A. Strójwąs (PDF Solutions and Carnegie Mellon Univ., USA), K. Doong, D. Ciplickas (PDF Solutions, USA)

Layout Design Rules have been scaled very aggressively to enable 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to the overlay tolerances and diminishing process windows, reliability risks due to soft shorts/leakages and soft open for both FEOL and BEOL have also increased to a critical level. Introduction of EUV at the second wave of 7nm and 5nm will not help a lot because of the defectivity and significant increase in Local Edge Roughness. New characterization techniques are necessary to identify the yield and reliability risks. After reviewing the design rule evolution and classifying the yield and reliability risks, we will present examples from the Design For Inspection (DFI) and novel VarScan methodology to “detect the undetectable” defects and characterize the variability for both FEOL and BEOL 7nm and below technologies