Conference paper

Low Power Design From Moore to AI for nm Era (Invited Paper)

R.V. Joshi, M. Ziegler (IBM Research Division, USA)

Power has become the key driving force in processor design as the frequency scale-up is reaching saturation. In order to achieve low power system circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates. However, Moore’s law driving the advancement in semiconductor industry over decades has been coming to a screeching halt and many researchers are convinced that it is almost dead. After revival and Fpromise of artificial intelligence (AI) due to increased computational performance and memory bandwidth aided by Moore’s law there is overwhelming enthusiasm in researchers for increasing the pace of VLSI industry. AI uses many neural network techniques for computation which involves training and inference. The advancement in AI requires energy efficient, low power hardware systems. This is more so for servers, main processors, Internet of Things (IoT) and System on chip (SOC) applications and newer applications in cognitive computing. This talk describes pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-14nm era, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power, leakage power, short circuit power and collision power are covered. Usage of clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and other methods are described for logic and memory. In addition novel ideas are developed and applied to memories and peripheral logic. The near threshold voltage (NTV) operation of 8T cells in 14nm FinFET SOI technology is explored. A number of enhancements to the recently proposed voltage supply boosting techniques are proposed. These improvements allow a reduction in the power required for boosting through optimizing boost buffer sizes and shaping the boost pulse, using programmable boost signal techniques. We also present new hardware measurements that show voltage supply boosting can allow SRAM Vmin reduction close to 0.3V in 14nm technology. Finally the talk summarizes key challenges in achieving low power.

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Receipt of papers:

March 1st, 2021

Notification of acceptance:

April 26th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 17th, 2021