Conference paper

Relocatable Partial Bitstreams for Overlay Architectures atop FPGAs

Z. Mudza (Lodz Univ. of Techn., Poland)

Intermediate virtual architecture overlays atop physical FPGA chips provide convenient abstraction level, which can increase productivity in FPGA-targeted application development. Individual reconfigurable modules of the overlay can be reprogrammed independently using partial reconfiguration. Homogeneous reconfigurable modules can be programmed using common configuration data, on condition that appropriate implementation constraints and proper floorplanning of the virtual architecture are provided. This paper presents methodology that can be used to generate relocatable bitstreams for Xilinx 7-series FPGA devices. The methodology is based on using constraints to force Xilinx Vivado Design Suite tools to implement multiple reconfigurable partition in the same way. Partial Reconfiguration Flow is used to implement multiple variants of individually reconfigurable partitions and Isolation Design Flow is used for feed-through prevention.

Download one page abstract

Receipt of papers:

March 13th, 2020

Notification of acceptance:

May 18th, 2020

Registration opening:

May 20th, 2020

Final paper versions:

June 5th, 2020