Conference paper

Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC

T. Stefanski (Gdansk Univ. of Techn., Poland), K. Rudnicki (Brightelligence Sp. z o.o., Poland), W. Żebrowski (Aldec Inc., Gdansk Office, Poland)

Recently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this paper, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multi-processor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). For sufficiently large input parameters, a single coprocessor is up to 4.5 times faster than a single CPU core within the same chip emulating MPA using a software library.

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Receipt of papers:

March 15th, 2021

Notification of acceptance:

May 11th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 31th, 2021