Conference paper

Queuing Parallel Computing CAD Tasks in the Design and Optimization of IC Topography

A. Wojtasik (Warsaw Univ. of Techn., Poland)

In recent years, the development of personal computers hardware has been aimed at increasing the number of processor cores. At the same time, the efficiency and reliability of computer interconnecting networks is increased. This enables the introduction and development of parallel and distributed processing methods also in CAD systems. The paper presents the problems related to the parallelization of the computational process and the methods of solving them, based on the example of typical computational experiments used in the design and optimization of integrated circuits topography.

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Receipt of papers:

March 15th, 2021

Notification of acceptance:

May 11th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 31th, 2021