Conference paper

Class AB Operational Amplifier in CMOS 55 nm Technology

P. Pieńczuk (Łukasiewicz Research Network - Inst. of Microel. and Photonics, Poland), W.A. Pleskacz (Warsaw Univ. of Techn., Poland), M. Teodorowski (OmniChip Sp. z o.o., Poland)

A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67º ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.

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Receipt of papers:

March 15th, 2021

Notification of acceptance:

May 11th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 31th, 2021