Conference paper

Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits

A. Wojciechowski (Warsaw Univ. of Techn., Poland), K. Marcinek (Warsaw Univ. of Techn. and ChipCraft Sp. z o.o., Poland), W. Pleskacz (Warsaw Univ. of Techn., Poland)

Phase difference of the clock signals is a critical factor in high precision synchronization of interconnected integrated circuits. In order to synchronize a daisy-chained set of individual systems, a novel concept of clock signal phase alignment circuit as well as calibration algorithm were developed. The work describes a high-level analog circuit and the calibration procedure implemented in the digital control module. The high-level implementation was tested using Verilog HDL language and conclusions are presented. Moreover, the required features and recognized restrictions are also discussed.

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Receipt of papers:

March 15th, 2022

Notification of acceptance:

April 30th, 2022

Registration opening:

May 12th, 2022

Final paper versions:

May 20th, 2022