Conference paper

Advances in Qucs-S Schematic Capture for SPICE and Verilog-A Device Modelling and Circuit Simulation

M. Brinson (London Metropolitan Univ., UK), D. Tomaszewski (Institute of Microelectronics and Photonics, Poland)

Schematic capture is an important and popular front-end for circuit simulation. It provides users with a flexible tool that allows circuit diagrams to be drawn and automatically converted into textual circuit netlists. Conventional SPICE simulators are essentially engines that input circuit data and simulation command netlists, undertake simulation, and output data for post-processing. This paper is concerned with an advance in circuit schematic capture functionality which allows both SPICE netlists and Verilog-A module code to be simultaneously generated from a device model or circuit schematic. This development, particularly when combined with SPICE behavioural device modelling, allows automatic generation of Verilog-A device modules rather than going through the manual conversion process from SPICE netlists to Verilog-A code modules. To demonstrate the validity of the reported advances in Qucs-S/Xyce schematic capture a behavioural model and a Verilog-A module for a GaAs MESFET are presented, and their performance described.

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Receipt of papers:

March 15th, 2023

Notification of acceptance:

April 30th, 2023

Registration opening:

May 15th, 2023

Final paper versions:

May 15th, 2023