IC Masks - The Challenges of the Newest Technologies

M. Niewczas (D2S Inc., USA)

The mask technology for the 5nm node and below, has become more complex and expensive. This is because two significant advances were unavoidable. First, the introduction of EUV lithography scanners allowed to create smaller shapes on wafer comparing with the 193i lithography. Second, the arrival of Multi-Beam Mask Writers (MBMW) allows to write much more complex masks than the VSB machines. We start with description of the construction of the EUV mask and the principles of operation of EUV scanner and MBMW. We review various topics that the mask industry deals with today: modeling of mask and lithography processes, mask inspection and repair, data volume explosion. Then, we focus on what happens between the design tape-out and writing of the physical mask: Optical Proximity Correction (OPC) and Mask Data Preparation (MDP). We present examples of current research and describe supercomputing on GPU clusters, the third hidden factor that makes some of the algorithms possible. Finally, we discuss the expected transition to curvilinear geometry. Comparing with Manhattan or octagonal shapes, it leads to smaller layouts, better performance, and improved process window. However, transition is difficult and controversial: the software infrastructure for design and manufacturing requires significant modifications.