Conference paper

Multidomain Modeling for Reliability Evaluation of Devices and Microsystems Using Verilog-A

J.-B. Kammerer, M. Garci, F. Prégaldiny, L. Hébrard (ICube, France), A. Kaïd, F. Roqueta (STMicroelectronics, France)

With the continuous increase in integration density, the dissipated power density has reached a critical level and thermal issues are now a major concern. Currently, evaluating the thermal behavior of a chip is generally done thanks to a finite element method software. However, this approach is complex, time consuming and sometimes even not feasible. Thereby, the need for a user-friendly tool designed to evaluate the temperature distribution inside an integrated system through standard circuit simulation arises. Hardware description languages (HDL) offer the opportunity to manipulate thermal quantities thus allowing to perform electrothermal simulations in a standard microelectronics CAD environment. Taking advantage of the capabilities of these HDL, a general methodology consisting in layout driven meshing for thermal modeling of the chip associated to electrothermal compact modeling of devices has been developed. The resulting tool which is fully integrated in the Cadence environement is able to generate an electrothermal netlist suitable to SPICE-like simulators. To address large system simulations, a high-level electrothermal modeling method has been developed, allowing to perform full-chip simulations. Recently, that tool has been adapted to power electronics industry needs. It is able to address reliability issues such as overheating, hot spot detection or thermal drift.

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Receipt of papers:

March 15th, 2022

Notification of acceptance:

April 30th, 2022

Registration opening:

May 12th, 2022

Final paper versions:

May 20th, 2022