Conference paper

Compensation of Temperature Nonlinearity in a Zener-Based Voltage Reference

V. Bucur, G. Banarie (Analog Devices International, Ireland), S. Marinca (Tech. Univ. of Cluj-Napoca, Romania)

There is an increasing demand for high-performance, low-cost, small footprint, reliable silicon-based voltage references. A circuit architecture incorporating all the above criteria was developed and presented in [1], [2], [3]. One major architectural performance limitation common to all, was their ability to mitigate only the 1st order temperature dependency of the Zener Diode used to generate the voltage reference. While incorporating the learning from [4] and [5], this paper proposes a novel compensation technique, capable of correcting independently both the 1st, and the 2nd order coefficients of the temperature dependency associated with any Zener-based voltage reference with thermally uncompensated substrate, thus allowing the trade-off between noise and power without sacrificing temperature stability. The circuit is currently in full prototype development stage. Throughout all process corners, a temperature coefficient of maximum 0.7ppm/°C was simulated for the proposed circuit.

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Receipt of papers:

March 15th, 2023

Notification of acceptance:

April 30th, 2023

Registration opening:

May 15th, 2023

Final paper versions:

May 15th, 2023