Conference paper

Design, Verification and Testing of a Readout Integrated Circuit for Hybrid Pixel X-ray Detectors with in-Pixel Time Measurement Functionality in 28 nm CMOS

L.A. Kadlubowski (AGH Univ. of Science and Techn. in Krakow, Poland)

This paper summarizes the design of a prototype integrated circuit for hybrid pixel X-ray detectors fabricated in 28 nm CMOS technology. The chip consists of 32 pixels with dimensions 50 μm × 50 μm each. Each pixel is divided into three sections: a front-end, two-ring oscillators with their frequency control circuits and a digital part. It offers single-photon counting functionality as well as in-pixel time measurement. In previous papers, a detailed design of the chip and simulation results were reported and an approach was described that utilized SystemVerilog language together with AMS simulator for the verification of this asynchronous, mixed-mode circuitry. This paper focuses more on testing fabricated chips. It describes a test setup and PCB design and mentions how the prior SystemVerilog verification approach helped with the development of a testing software. Finally, preliminary measurement results are presented that illustrate the performance of front-end and oscillators.

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Receipt of papers:

March 15th, 2023

Notification of acceptance:

April 30th, 2023

Registration opening:

May 15th, 2023

Final paper versions:

May 15th, 2023