A Method for Implementing a SHA256 Hardware Accelerator inside a Quantum True Random Number Generator (QTRNG)

K. Witek (AGH Univ. of Science and Techn. in Krakow, Poland), M. Caccia (Univ. degli Studi dell'Insubria, Italy), W. Kucewicz, M. Baszczyk, P. Dorosz (AGH Univ. of Science and Techn. in Krakow, Poland), Ł. Mik (Univ. of Applied Sciences in Tarnow, Poland)

Availability of streams of random numbers is critical in a number of significant applications. e.g. computer security and cryptography, privacy preservation procedures, IoT secure communication, numerical simulation of complex phenomena, gaming and gambling. Random number generation can be based on algorithms or on observables related to unpredictable natural phenomena. Algorithms are deterministic therefore the randomness properties of the generated sequences is irreducibly limited. Hardware generation of random numbers, especially when based in quantum phenomena, is made unbreakable by the same laws of nature, thus Random Power is focusing on the development of a Quantum-True Random Number generation (QTRNG) platform, producing unpredictable bit streams analysing the time series of self-amplified endogenous pulses due to stochastically generated in a dedicated Silicon device. As per NIST recommendations, a SHA256 conditioning function was used in order to reduce potential biases and guarantee the required level of entropy. This paper reports the firmware development and implementation of a real-time SHA256 accelerator, which is capable of generating bits in bursts at a maximum rate of 170Mbps. Prepared software allows users to perform on demand self tests and co-validation of accelerator’s results. For the latter one, a software SHA256 implementation calculates message digests (from random bits) and compares them to the corresponding message digests generated by hardware.