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Conference paper

Full-SiC Single-Chip Buck and Boost MOSFET-JBS Converters for Ultimate Efficient Power Vertical Integration

R. Makhoul (LAAS-CNRS Toulouse and Ampere INSA Lyon, France), A. Bourennane (LAAS-CNRS Toulouse, France), L.V. Phung (Ampere INSA Lyon, France), F. Richardeau (LAPLACE Toulouse, France), M. Lazar, N. Beydoun, S. Kostcheev (Technological Univ. of Troyes, France), P. Godignon (IMB-CNM Barcelona, Spain), D. Planson, H. Morel (Ampere INSA Lyon, France), D. Bourrier (LAAS-CNRS Toulouse, France)

This paper aims at demonstrating the relevance of a new design perimeter for power switching cells through a monolithic vertical integration approach on a multi-terminal power chip with Wide-Band Gap material such as 4H silicon carbide (SiC). Multi-terminal monolithic architectures making use quasi-only of vertical unipolar switch (VDMOS) and JBS diode architecture within the context of a 600V/10A full integration of switching cells on 4H-SiC chips are proposed and validated through Sentaurus 2D numerical simulations. The key method to etch and to fill the metallic via neededto connect the VDMOS and the JBS from top to back side of the SiC wafer is presented. The first optimization of the electroplating process resulted in a Ni metal layer of about 5µm thick.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024