Conference paper

Successful Selection of the SoC Clocking Architecture

K. Kasiński (AGH Univ. of Science and Techn. in Krakow and Silicon Creations sp. z o.o., Poland), D. Ziółkowski, P. Banachowicz, J. Iwanicka (Silicon Creations sp. z o.o, Poland)

Each custom ASIC / SoC products is different and has specific requirements for the selected clock generation solution. Depending on the application, necessary decision must be made regarding different trade-off present in the integrated circuit design. This paper summarizes the key aspects of proper selection of the digital clocking solution to achieve the desired performance. From requirements, such as reference frequency source choice, through PLL selection and configuration to the integration in the final product. Key performance indicators - including the most common: jitter, power, area - and methods to balance them are discussed.

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Receipt of papers:

March 15th, 2023

Notification of acceptance:

April 30th, 2023

Registration opening:

May 15th, 2023

Final paper versions:

May 15th, 2023