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Conference paper

Ethernet-based In-System Testing and Utilization of IP Cores Implemented on FPGA Development Kits

V.D. Damnjanović (Univ. of Belgrade and NOVELIC, Serbia), V.M. Milovanović (Univ. of Kragujevac and NOVELIC, Serbia)

In modern embedded system applications, hardware acceleration of complex software algorithms is proven to be of great importance when it comes to performance enhancement and functionality realization, especially within systems with limited resources. On the other hand, testing a hardware module is not always straightforward, and a PC could have a crucial part in it. Therefore, this paper depicts a methodology for testing and debugging various hardware modules implemented on an FPGA platform with the Ethernet 8P8C port, as well as for utilizing some of its advantages while being integrated into an embedded system. It is achieved using a parameterizable generator, implemented mainly using Chisel hardware design language. The proposed generator provides instances of hardware modules connected to both the Ethernet 8P8C port and the AXI4 or AXI4-Stream bus, thus serving as a bridge and allowing the two-way communication between the other modules implemented in hardware and connected to the bus (e.g. algorithm acceleration module), and an external device with the Ethernet port, namely a PC. The design was tested by implementing different generated instances within appropriate systems, consisting of commercial FPGA-based boards and PC-run Python applications. It was shown on multiple examples that it could greatly help in testing and utilizing hardware modules and their capabilities, even on relatively low-priced FPGA devices.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024