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Conference paper

A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems

G. Di Patrizio Stanchieri, A. De Marcellis, M. Faccio, E. Palange (Univ. of L'Aquila, Italy), O. Aiello (Univ. of Genoa, Italy)

This paper reports on a Duty-Cycle Corrector (DCC) circuit that employs a closed-loop scheme paradigm capable to provide a real time 50% duty-cycle control of the generated output clock signal. A control voltage generated by a feedback circuit allows to estimate the values of the duty-cycles of the input and output clock signals. This control voltage provides and regulates the values of two currents that charge and discharge, even asymmetrically, a load to adjust the output clock signal duty-cycle. The DCC circuit has been designed in TSMC 180 nm CMOS technology with a 1.8 V single supply voltage, requires a total Si area of about 0.017 mm^2 with a power consumption of 0.46 mW/GHz. The reported post-layout simulations validated the DCC circuit performances to suitable correct the input clock signal duty-cycle for values ranging from 30 % to 70 % so providing a 50 % duty-cycle of the output clock signal with an error smaller than ±1 %. Furthermore, the proposed simple DCC circuit handles input clock waveforms with frequencies ranging from 3 GHz down to 30 kHz. This makes the DDC circuit suitable for a variety of applications such as clock generators, transceivers, serial interfaces, Phase-Locked Loop, Delay-Locked Loop, RAM memories, and data links.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024