1S1R Sub-threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation

J. Minguet Lopez, M. Dampfhoffer, T. Hirtzlin, L. Reganaz, L. Grenouillet, G. Navarro, M. Bernard, T. Magis, C. Carabasse, N. Castellani, V. Meli, E. Vianello (CEA-Leti, Univ. Grenoble Alpes, France), D. Deleruyelle (INL CNRS, INSA Lyon, France), J. Portal (Aix Marseille Univ., CNRS, IM2NP, France), G. Molas (Weebit Nano Ltd., France), F. Andrieu (CEA-Leti, Univ. Grenoble Alpes, France)

Single memristor Crossbar array integration on computing core units is a very promising approach to significantly reduce the latency and power consumption of deep learning accelerators, enhancing their deployment on embedded systems. In this context, Deep Neural Networks (DNNs) synaptic weight hardware implementation using non-volatile emerging neuromorphic memory devices is one of the most promising strategies. However, the intrinsic operating variability of the emerging memory devices can severely limit the overall network performance. To address this challenge, both memory device and Neural Network optimization are primordial. On one hand, developing highly performant novel emerging memory devices with reliable operating characteristics remains essential. On the other hand, engineering the Neural Network characteristics at the algorithm and design level is key to optimize the overall circuit tolerance to hardware non-idealities. In this paper, the co-integration between a HfO2-based OxRAM memory device (1R) and an Ovonic Threshold Switch (OTS) selector (1S) in high-density 1S1R Crossbar arrays is proposed. Its utilization on Neural Network hardware-implemented circuits is addressed. First, the 1S1R device operating characteristics are elucidated. Based on this analysis, 1S1R figures of merit for Neural Network hardware implementation are discussed, based on both OTS and OxRAM devices electrical features. On one hand, 1S1R cell downscaling is demonstrated to improve the device insulating properties with no counterpart in terms of switching voltages. Notably, this allows improving the overall memory capacity while preserving limited electrical consumption. On the other hand, 1S1R highly parallelized reading capabilities in Crossbar arrays are demonstrated. Remarkably, this enables the optimization of the overall computation latency while preserving reasonable bit error rate. Second, the standard Binarized Neural Networks (BNNs) and bio-inspired Binarized Spiking Neural Networks (BSNNs) robustness to 1S1R non-idealities is studied. Notably, both Neural Networks show good tolerance to memory device non-idealities, validating the pertinence of OxRAM+OTS Crossbar arrays for synaptic weight encoding. All in all, the OxRAM+OTS Crossbar arrays potential for neuromorphic applications is elucidated, opening the way for a system-level investigation towards specific applications. Moreover, the need to carry out a parallel co-development between the memory device and the Neural Network characteristics to optimize the overall circuit performance is illustrated.