A Pathfinding PDK Toward 10nm FD-SOI Technology

O. Billoint, M. Alepidis, Y. Andee, K. Azizi-Mourier, A. Boujnah, P. Chausse, H. Chazot-Ranquet, J.-F. Christmann, O. Cueto, E. De-Foucauld, H. Jacquinot, J. Lacord, G. Largiller, D. Ly, Y. Maneglia, M. Mouhdach, A.-A. Ndiaye, O. Rozeau, A. Vaysset, T. Poiroux (Univ. Grenoble Alpes, France)

The FAMES pilot line is a unique opportunity for Europe to promote advanced semiconductor technologies, one of its objectives being to develop a pathfinding PDK for a future 10nm FD-SOI process technology. This work will describe the path taken from the first process assumptions to designing standard cells libraries and delivering the PDK, with an emphasis on existing FD-SOI technologies, key design rules, associated layout constraints on standard cells topology, Design Technology Co Optimization (DTCO) and validation of the PDK on different designs.