MIXDES - The MIXDES 2007 information

14th International Conference
Mixed Design of Integrated Circuits and Systems
Ciechocinek, 21-23 June 2008

The MIXDES 2007 Conference took place in Ciechocinek, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Embedded Systems
  9. Medical Applications
  10. Information Technology
  11. Education

The total number of 130 papers from 33 countries were accepted for publication including 5 invited papers.

The following invited papers were presented during the conference:

  1. Evolution of the Classical Functional Integration Towards a 3D Heterogeneous Functional Integration, J.-L. Sanchez, A. Bourennane, M. Breil, P. Austin, M. Brunet, J.P. Laur (LAAS-CNRS and Univ. Toulouse, FRANCE)
  2. Modelling of Thin Film Transistors for Circuit Simulation, B. Iniguez (Univ. Rovira i Virgili, SPAIN), R. Picos (Univ. Illes Balears, SPAIN), M. Estrada, A. Cerdeira (CINVESTAV, MEXICO), T.A. Ytterdal (Norwegian Univ. of Science and Techn., NORWAY), W. Jackson (HP Labs, USA), A. Koudymov, D. Veksler, M.S. Shur (Rensselaer Polytechnic Inst., USA)
  3. STARC's Semiconductor Design Technology Research Activities and the HiSIM2 Advanced MOSFET Model Project, Y. Furui (STARC, JAPAN), M. Miura-Mattausch, N. Sadachika, M. Miyake, T. Ezaki, H.J. Mattausch (Hiroshima Univ., JAPAN), T. Ohguro, T. Iizuka, R. Inagaki, N. Fudanuki (STARC, JAPAN)
  4. Tradeoffs and Optimization in Analog CMOS Design, D.M. Binkley (The Univ. of North Carolina at Charlotte, USA)

The following special sessions were organised during the conference:

  1. Compact Modelling Special Session
    • Development of MPW Service for Academies Based on ITE Proprietary CMOS Process, D. Obrębski, K. Kucharski, M. Grodner, A. Kokoszka, A. Malinowski, J. Lesiński, D. Tomaszewski, J. Malesińska (Institute of Electron Techn., POLAND)
    • EKV3 Parameter Extraction and Characterization of 90nm RF-CMOS Technology, S. Yoshitomi (Toshiba Corp. Semiconductor Company, JAPAN), A. Bazigos (National Tech. Univ. Athens, GREECE), M. Bucher (Tech. Univ. Crete, GREECE)
    • Electrical Characteristics in n- and p-MOSFETs with Slightly Tilted Off-axis (110) Channel, H.S. Momose, S. Yoshitomi, K. Kojima, T. Ohguro, Y. Toyoshima (Toshiba Corp. Semiconductor Company, JAPAN), H. Ishiuchi (Toshiba Corp. Research and Development Center, JAPAN)
    • Experiments and Modeling of Dynamic Floating Body Effects in 1T-DRAM Fully Depleted SOI Devices, M. Bawedin (Univ. Catholique de Louvain, BELGIUM and INPG, FRANCE), S. Cristoloveanu (INPG, FRANCE), V. Dessard (CISSOID, BELGIUM), D. Flandre (Univ. Catholique de Louvain, BELGIUM)
    • Model Parameter Extraction for the High Voltage SOI-Process Using BSIMSOI3 Model and ICCAP, J. Pieczynski (Fraunhofer Inst. for Microelectronic Circuits and Systems, GERMANY), T. Gneiting (AdMOS GmbH Advanced Modeling Solutions, GERMANY)
    • Structured Design Based on the Inversion Factor Parameter: Case Study of ΔΣ Modulator System, D. Stefanovic (EPFL, SWITZERLAND), S. Pesenti (Marvell Semiconductor, SWITZERLAND), M. Pastre, M. Kayal (EPFL, SWITZERLAND)
  2. Advanced Logic Synthesis with Application to FPGA-based Implementations
    • Distributed Arithmetic Based Implementation of Fourier Transform Targeted at FPGA Architectures, M. Rawski, M. Wojtyński, T. Wojciechowski, P. Majkowski (Warsaw Univ. of Techn., POLAND)
    • Logic Synthesis Importance in FPGA-based Designing of Image and Signal Processing Systems, P. Tomaszewicz, M. Nowicka (Warsaw Univ. of Techn., POLAND), B.J. Falkowski (Nanyang Techn. Univ., SINGAPORE), T. Łuba (Warsaw Univ. of Techn., POLAND)
    • Programmable Hardware Implementation Based on Four Walsh Sequences, B.J. Falkowski (Nanyang Techn. Univ., SINGAPORE), T. Sasao (Kyushu Inst. of Techn., JAPAN), T. Łuba (Warsaw Univ. of Techn., POLAND)
    • Reconfigurable FPGA-based Hardware Accelerator for Embedded DSP, G. Rubin, M. Omieljanowicz, A. Petrovsky (Bialystok Tech. Univ., POLAND)
    • Synthesis of Control Unit with Modified Microinstructions, A. Barkalov, L. Titarenko, J. Bieganowski (Univ. Zielona Góra, POLAND)
  3. CARE Project Special Session
    • A Novel Approach for Hardware Implementation of a Detuning Compensation Control System for SC Cavities, K. Przygoda (Tech. Univ. Lodz , POLAND), R. Paparella (Univ. degli Studi di Milano, ITALY)
    • In Situ Measurement of Neutron and Gamma Radiation Exposures During Intercontinental Flights Using Electronic Personal Dosimeter and Bubble Detectors, B. Mukherjee (Deutsches Elektronen-Synchrotron, GERMANY), D. Makowski (Tech. Univ. Lodz, POLAND), V. Mares (GSF-National Research Centre, GERMANY), D. Rybka (Warsaw Univ. of Techn., POLAND), S. Simrock (Deutsches Elektronen-Synchrotron, GERMANY)
    • Integral Interface - Universal Communication Interface for FPGA-based Projects, A. Piotrowski, S. Tarnowski, G. Jabłoński, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Low-latency Implementation of Coordinate Conversion in Virtex II Pro FPGA, G. Jabłoński, K. Przygoda (Tech. Univ. Lodz, POLAND)
    • RadTest - Testing Board for the Software Implemented Hardware Fault Tolerance Research, A. Piotrowski, D. Makowski, S. Tarnowski, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Sinusoidal Signal Synthesis from Vector Values with Small Quantity of Samples, S. Tarnowski, A. Piotrowski, A. Napieralski (Tech. Univ. Lodz, POLAND)

The following papers has been awarded:

  • Outstanding Paper Award was presented to:
    • A Low-power Strategy for Delta-Sigma Modulators, S. Pesenti, P. Clement (Marvell Semiconductor, SWITZERLAND), D. Stefanovic, M. Kayal (EPFL, SWITZERLAND)
    • Application of Advanced Thermal Analysis Method for Investigation of Internal Package Structure, J. Banaszczyk (Ghent Univ., BELGIUM), M. Janicki (Tech. Univ. Lodz, POLAND), B. Vermeersch, G. De Mey (Ghent Univ., BELGIUM), A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Application of RC Equivalent Networks to Modelling of Nonlinear Thermal Phenomena, M. Kamiński, M. Janicki, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Comparison of Two Pole-Zero Cancellation Circuits for Fast Charge Sensitive Amplifier in CMOS Technology, P. Gryboś, P. Maj, R. Szczygieł (AGH Univ. of Science and Techn., POLAND)
    • Configurable High Side Power Switch in Smart Power Technology, P. Del Croce, J. Hadzi Vukovic, B. Meldt, M. Ladurner (Infineon, AUSTRIA)
    • CPLD Based Development Board for Mixed Signal Chip Testing, P. Śniatała, J. Pierzchlewski, A. Handkiewicz (Poznan Univ. of Techn., POLAND), B. Nowakowski (Atrem Sp. z o.o., POLAND)
    • Eyelids Localization Method Designed for Iris Recognition System, W. Sankowski, K. Grabowski, M. Napieralska, M. Zubert (Tech. Univ. Lodz, POLAND)
    • Facet Heating Mechanisms in High Power Semiconductor Lasers Investigated by Spatially Resolved Thermoreflectance, D. Pierścińska, K. Pierściński, A. Kozłowska (Institute of Electron Techn., POLAND), A. Maląg (Inst. of Electronic Materials Techn., POLAND), A. Jasik, M. Bugajski (Institute of Electron Techn., POLAND)
    • Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35um HV CMOS Technology, W. Pflanzl, E. Seebacher (austriamicrosystems AG, AUSTRIA)
    • Mixed-mode Simulation and Analysis of Digital Single Event Transients in Fast CMOS ICs, M. Turowski, A. Raman (CFDRC, USA), G. Jabłoński (Tech. Univ. Lodz, POLAND)
    • Superscalar MOVE Architecture for Power-aware Computing, A. Łuczyk (Warsaw Univ. of Techn., POLAND)
    • Thermal Imaging of Actively Cooled High-power Laser Bars, A. Kozłowska (Institute of Electron Techn., POLAND), M. Ziegler, J.W. Tomm (Max Born Inst., GERMANY), R.P. Sarzała, W. Nakwaski (Tech. Univ. Lodz, POLAND)
    • Wavelet Processing Implementation in Digital Hardware, P.M. Szecówka, M. Kowalski, K. Krysztoforski, A.R. Wołczowski (Wrocław Univ. of Techn., POLAND)
  • Poland Section IEEE ED Chapter Special Award was presented to:
    • Hardware Fault Free Simulation for SoC, V. Hahanov, M. Kaminska, W. Ghribi, A. Hahanova (Kharkov National Univ. of Radioel., UKRAINE)

Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024