MIXDES - The MIXDES 2009 information

16th International Conference
Mixed Design of Integrated Circuits and Systems
Łódź, 25-27 June 2009

The MIXDES 2009 Conference took place in Łódź, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Embedded Systems
  9. Medical Applications

The total number of 147 papers from 27 countries were accepted for publication including 4 invited papers.

The following invited papers were presented during the conference:

  1. A 0.13 µm SiGe BiCMOS Technology for mm-Wave Mixed-Signal Applications, H. Ruecker, B. Heinemann, A. Mai, B. Tillack (IHP, GERMANY)
  2. Comparison of Fault-Tolerance Techniques for Massively Defective Fine- and Coarse-Grained Nanochips, J.H. Collet (LAAS-CNRS, FRANCE), M. Psarakis (Univ. Piraeus, GREECE), P. Zając (Tech. Univ. Łódź, POLAND), D. Gizopoulos (Univ. Piraeus, GREECE), A. Napieralski (Tech. Univ. Łódź, POLAND)
  3. The EKV3 MOS Transistor Model for RF Circuit Simulation, M. Bucher, M.-A. Chalkiadaki (Tech. Univ. Crete, GREECE), A. Bazigos (National Tech. Univ. Athens, GREECE)
  4. Virtual Experiments at the Rim of the Safe-Operating Area of Power Devices, G. Wachutka (Tech. Univ. München, GERMANY)

The following special sessions were organised during the conference:

  1. Device Level Support for Emerging CMOS Technologies (Special Session)
    • Analysis of 3D Current Flow in Undoped FinFETs and Approaches for Compact Modeling, A. Kloes, M. Weidemann, M. Schwarz (Univ. Applied Sciences Giessen, GERMANY)
    • Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator, M. Brinson (London Met. Univ., UK), S. Jahn (Qucs project manager, Munich, GERMANY)
    • Continuous Compact Model for MuGFETs Simulations, J. Alvarado, V. Kilchytska, D. Flandre (Univ. Louvain, BELGIUM), J. Conde, M. Estrada, A. Cerdeira (CINVESTAV-IPN, MEXICO)
    • Design of Pixel Readout Integrated Circuits in Submicron Technology to Minimize the Mismatch Effects, R. Szczygieł, P. Gryboś, P. Maj (AGH Univ. of Science and Techn., POLAND)
    • FinFET Compact Modeling and Parameter Extraction, N. Chevillon, M. Tang, F. Prégaldiny, C. Lallement, M. Madec (InESS / UdS, FRANCE)
    • Fluctuations of Electrical Characteristics of FinFET Devices, D. Tomaszewski, A. Malinowski (Institute of Electron Techn., POLAND), P. Sałek, L. Łukasiak (Warsaw Univ. of Techn., POLAND), M. Zaborowski (Institute of Electron Techn., POLAND), A. Jakubowski (Warsaw Univ. of Techn., POLAND)
    • Global Extraction of MOSFET Parameters Using the EKV Model: Some Properties of the Underlying Optimization Task, J. Arabas, L. Bartnik, S. Szostak (Warsaw Univ. of Techn., POLAND), D. Tomaszewski (Institute of Electron Techn., POLAND)
    • Risk Management of LSI Design by Spice Parameter QA Methodology, H. Koike (STARC, JAPAN), S. Ito (Seiko Epson Corp., JAPAN), H. Masuda (Renesas Technology Corp., JAPAN), N. Wakita (Toshiba Corp., JAPAN), R. Inagaki (ROHM Co., Ltd., JAPAN)
    • The Surface-Potential-Based Compact Model HiSIM-SOI for Silicon-On-Insulator MOSFETs, H.J. Mattausch, N. Sadachika, S. Kusu, K. Ishimura, T. Murakami, M. Ando, M. Miura-Mattausch (Hiroshima Univ., JAPAN)
  2. EuCARD (Special Session)
    • A Novel Approach for Automatic Control of Piezoelectric Elements Used for Lorentz Force Detuning Compensation, K. Przygoda, T. Poźniak, A. Napieralski (Tech. Univ. Łódź, POLAND), M. Grecki (DESY, GERMANY)
    • Compiler-level Implementation of Single Event Upset Errors Mitigation Algorithms, A. Piotrowski, S. Tarnowski (Tech. Univ. Łódź, POLAND)
    • Development and Tests of PWM Amplifier for Driving the Piezoelectric Elements, J. Matiulko, T. Poźniak, K. Przygoda (Tech. Univ. Łódź, POLAND), M. Grecki (DESY, GERMANY)
    • Diagnostic Application for Development of Custom ATCA Carrier Board for LLRF, J. Wychowaniak, P. Predki, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Digital Vector Modulator with Diagnostic Circuit for Particle Accelerator, S. Tarnowski, A. Piotrowski (Tech. Univ. Łódź, POLAND)
    • Distributed Radiation Monitoring System for Linear Accelerators Based on CAN Bus, T. Kozak, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Evaluation of an ATCA Based LLRF System at FLASH, S. Simrock, M. Grecki, T. Jeżyński, W. Koprek (DESY, GERMANY), Ł. Butkowski (DESY, POLAND), G. Jabłoński, W. Jałmużna, D. Makowski, A. Piotrowski (Tech. Univ. Łódź, POLAND), K. Czuba (Warsaw Univ. of Techn., POLAND)
    • High Power Amplifiers Chain Nonlinearity Influence on the Accelerating Beam Stability in a Free Electron Laser (FLASH), W. Cichalewski, W. Jałmużna (Tech. Univ. Łódź, POLAND)
    • Hot-plug Based Activation and Deactivation of ATCA FRU Devices, P. Prędki, D. Makowski (Tech. Univ. Łódź, POLAND)
    • Improvements of SEU Tolerance by Spatial Redundancy in Digital Circuits, M. Grecki (DESY, GERMANY), G. Jabłoński, D. Makowski (Tech. Univ. Łódź, POLAND)
    • Klystron Lifetime Management System, Ł. Butkowski (Warsaw Univ. of Techn., POLAND), W. Koprek (DESY, GERMANY)
    • Multipurpose RF Field Vector Controller for Linear Accelerators, W. Jałmużna, W. Cichalewski (Tech. Univ. Łódź, POLAND), J. Szewiński (Institute for Nuclear Studies, POLAND)
    • PCIExpress Communication Layer for ATCA Based Linear Accelerator Control System, T. Kucharski, A. Piotrowski, D. Makowski, G. Jabłoński (Tech. Univ. Łódź, POLAND)
    • Software for Data Acquisition AMC Module with PCI Express Interface, S. Szachowałow, D. Makowski, G. Jabłoński, A. Napieralski (Tech. Univ. Łódź, POLAND), Ł. Butkowski (Warsaw Univ. of Techn., POLAND), W. Koprek, S. Simrock (DESY, GERMANY)
  3. PERPLEXUS (Special Session)
  4. The Future of Mobile and Embedded Systems (Special Session)
    • A Practical Approach to Performance Optimization of High-throughput Embedded Devices, M. Borzęcki (Proximetry Poland and Tech. Univ. Łódź, POLAND), Z. Chamski, K. Pawlak (Proximetry Poland, POLAND)
    • BlueMobi: Bluetooth Based Multi-domain Chat Application, R. Szczęsny (Teleca Poland Sp. z o.o., POLAND), B. Świercz, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Implementation of Cost-effective VoIP Network, M. Zasępa, P. Sękalski, B. Sakowicz, P. Mazur (Tech. Univ. Łódź, POLAND)
    • Mobile Remote Control Application for Power Generators Vibration Monitoring, P. Podsiadły (Teleca Poland Sp. z o.o., POLAND), B. Świercz, S. Wróblewski (Tech. Univ. Łódź, POLAND)
    • The Configurable Image Signal Processing Unit with Emphasis on Real Sensors Imperfection, P. Bicz (Tech. Univ. Łódź, POLAND), M. Baranowski (Teleca Poland Sp. z o.o., POLAND)
    • VNC-based Remote Control for Symbian OS Smartphones, A. Skurski, B. Świercz (Tech. Univ. Łódź, POLAND)
  5. Silicon Carbide Techology, Devices and Applications for High-temperature and High-power Electronics (Special Session)
    • Silicon Carbide - from Material Bulk Growth to Circuits and Applications, M. Sochacki, J. Szmidt (Warsaw Univ. of Techn., POLAND)
    • Stability of Al and Au Wire Bonds to Ti- and Ni-based Ohmic Contacts for High Power SiC Devices, R. Kisiel (Warsaw Univ. of Techn., POLAND), M. Guziewicz, A. Piotrowska (Institute of Electron Techn., POLAND), J. Szmidt (Warsaw Univ. of Techn., POLAND)
    • Structural Investigation of Silicon Carbide with Micro-Raman Spectroscopy, P. Borowicz, T. Gutt, T. Małachowski (Institute of Electron Techn., POLAND), P. Borowicz (Institute of Physical Chemistry, POLAND)
    • Three-phase Grid Inverter with SiC JFETs and Schottky Diodes, J. Rąbkowski, R. Barlik (Warsaw Univ. of Techn., POLAND)

The following papers has been awarded:

  • Outstanding Paper Award was presented to:
    • 2D Physics-based Compact Model for Channel Length Modulation in Lightly Doped DG FETs, M. Weidemann, A. Kloes, M. Schwarz (FH Giessen, GERMANY), B. Iniguez (Univ. Rovira i Virgili, SPAIN)
    • A Comparative Study on Transformer and Inductor Based LC Tanks for VCOs, R. Duarte, J. Fernandes (INESC-ID, PORTUGAL)
    • Digital Filter Implementation of Function Specification Inverse Algorithm, M. Janicki, Z. Kulesza, M. Szermer, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • High-Quality Factor MEMS Based Oscillator, F. Lo Conte, D. Grogg, A.M. Ionescu, M. Kayal (EPFL, SWITZERLAND)
    • Influence of the Intracavity Heatspreader on the VECSEL Temperature, K. Pierściński, D. Pierścińska, M. Bugajski (Institute of Electron Techn., POLAND), C. Manz, M. Rattunde (Institut fur Angewandte Festkorper Physik, GERMANY)
    • LNA, Oscillator and Mixer Co-Design for Compact RF-CMOS ISM Receivers, J. Oliveira, J. Ferreira, I. Bastos, L. Oliveira (UNINOVA/FCT, PORTUGAL), T. Michalak, P. Pankiewicz, P. Makoza, B. Nowacki, A. Rybarczyk (Poznań Univ. of Techn., POLAND)
    • Low Voltage Differential Signal Interface for Thermal Vision Camera, G. Bieszczad, T. Sosnowski, T. Orżanowski, M. Kastek (Military Univ. of Techn., POLAND)
    • Mixed-Mode Simulation of Single Event Upsets in Modern SiGe BiCMOS Mixed-Signal Circuits, M. Turowski, A. Raman, A. Fedoseyev (CFDRC, USA)
    • Numerically Controlled Oscillator with Spur Reduction, H.-J. Pfleiderer (Ulm Univ., GERMANY), S. Lachowicz (Edith Cowan Univ., AUSTRALIA)
    • Shutterless Method for Gain Nonuniformity Correction of Microbolometer Detectors, R. Olbrycht, B. Więcek, T. Świątczak (Tech. Univ. Łódź, POLAND)
    • Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism, S. Mendel (Graz Univ. of Techn., AUSTRIA), C. Vogel (ETH Zürich, SWITZERLAND), N. Da Dalt (Infineon Technologies Development Center, AUSTRIA)
    • SXDR64 – Multichannel Low Noise ASIC for CdTe and GaAs Detectors, M. Kachel, P. Gryboś, P. Kmon, R. Szczygieł (AGH Univ. of Science and Techn., POLAND)
    • Towards Hardware Implementation of bzip2 Data Compression Algorithm, P. Szecówka (Wrocław Univ. of Techn., POLAND), T. Mandrysz (Alder Techn. Park, Wrocław, POLAND)
  • Poland Section IEEE ED Chapter Special Award was presented to:
    • Logic Synthesis Strategy for FPGAs with Embedded Memory Blocks, M. Rawski, G. Borowik, T. Łuba, P. Tomaszewicz (Warsaw Univ. of Techn., POLAND), B. Falkowski (Nanyang Technological Univ., SINGAPORE)


Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024