MIXDES - The MIXDES 2011 information

18th International Conference
Mixed Design of Integrated Circuits and Systems
Gliwice, 16-18 June 2011

The MIXDES 2011 Conference took place in Gliwice, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Embedded Systems
  9. Medical Applications
  10. Student Projects

The total number of 128 papers from 27 countries were accepted for publication including 3 invited papers.

The following invited papers were presented during the conference:

  1. Design and Technology of High-Power Silicon Devices, J. Vobecký (Czech Tech. Univ. Prague, CZECH REPUBLIC)
  2. NeoSilicon Based Nanoelectromechanical Information Devices, S. Oda (Tokyo Inst. of Techn., JAPAN)
  3. Technology Challenges in Silicon Devices Beyond the 16 nm Node, M. Östling, J. Luo, V. Gudmundsson, P.-E. Hellström, B.G. Malm (Royal Inst. of Techn., SWEDEN)

The following special sessions were organised during the conference:

  1. Biomedical Engineering
    • Automatic Image Contrast Enhancement Method for Liver Vasculature Detection, M. Rudzki (Silesian Univ. of Techn., POLAND)
    • Center of Pressure Trajectory Segmentation for Postural Stability Analysis, J. Fiołka, Z. Kidoń (Silesian Univ. of Techn., POLAND)
    • CMOS Circuit for Detection of Neural Impulses, A. Jarosz, K. Zaraska, J. Wąsowski (Institute of Electron Techn., POLAND)
    • CT Images Processing as One of the Stages in Knee Joint Alloarthroplasty, P. Zarychta, J. Kawa (Silesian Univ. of Techn., POLAND)
    • Liver Surface Deformation Model for Minimally Invasive Surgery, M. Bugdol, J. Czajkowska (Silesian Univ. of Techn., POLAND)
    • Quantitative Tumour Tissue Measurements in Subjects with High-Grade Gliomas, P. Szwarc, J. Kawa, E. Piętka (Silesian Univ. of Techn., POLAND)
  2. Compact Modelling for Diagnostics and Design of Nanoscaled Analog ICs
    • Adaptive EPFL-EKV Long and Short Channel MOS Device Models for Qucs, SPICE and Modelica Circuit Simulation, M. Brinson, H. Nabijou (London Metropolitan Univ., UK)
    • Analysis of Selected Methods for CMOS Integrated Circuit Design for Yield Optimization, M. Yakupov, D. Tomaszewski (Institute of Electron Techn., POLAND)
    • Closed-Form Expressions for the Coupling Capacitance Computation Between Through Silicon Vias and Interconnects for 3D ICs, Y. Bontzios, M. Dimopoulos, A. Hatzopoulos (Aristotle Univ. Thessaloniki, GREECE)
    • Figure-of-Merit for Optimizing the Current-Efficiency of Low-Power RF Circuits, A. Mangla (EPFL, SWITZERLAND), C. Enz (EPFL and CSEM, SWITZERLAND), J.-M. Sallese (EPFL, SWITZERLAND)
    • Inversion Factor Based Design Methodology Using the EKV MOS Model, A. Ajbl, M. Pastre, M. Kayal (EPFL, SWITZERLAND)
    • Modeling of Parasitic Phenomena in Trench Technology, D. Prejda, J. Slezak, S. Banas (ON Semiconductor, CZECH REPUBLIC)
    • Modelling of Silicided and Blocked Poly-Si Resistors in 90 nm CMOS with the CMC-R2 Model, B. Landgraf (Infineon Techn. Austria AG, AUSTRIA), A. Vujasin (Tech. Univ. Graz, AUSTRIA), B. Ankele (Infineon Techn. Austria AG, AUSTRIA)
    • MOSFET Modeling for Simulation, Design and Optimization of Infrared CMOS Image Sensors Working at Cryogenic Temperature, P. Martin, F. Guellec (LETI, FRANCE)
    • PMOS Drain-Bulk Connected Loads for Subthreshold Source-Coupled Logic, I. Chlis, M. Bucher (Tech. Univ. Crete, GREECE)
    • Using the Light-impact Model for p-type and n-type Poly-TFT in Circuits, N. Papadopoulos, A. Hatzopoulos (Aristotle Univ. Thessaloniki, GREECE), D. Papakostas (Alexander Techn. & Edu. Inst. Thessaloniki, GREECE), R. Picos (Univ. Illes Balears, SPAIN), C. Dimitriadis (Aristotle Univ. Thessaloniki, GREECE)
  3. VESTIC: New VLSI Technology, Devices and Circuits
    • A Compact Model of VeSFET Capacitances, D. Kasprowicz (Warsaw Univ. of Techn., POLAND)
    • A Study on Cell-Level Routing for VeSFET Circuits, M. Marek-Sadowska, X. Qiu (Univ. California, USA)
    • Junction Vertical Slit Field-Effect Transistor (JVeSFET) - Compact DC Model, A. Pfitzner, M. Staniewski, M. Strzyga (Warsaw Univ. of Techn., POLAND)
    • Towards Circuit Design Using VeSFETs, M. Pastre, F. Krummenacher, M. Kayal (EPFL, SWITZERLAND)
    • Twin Gate, Vertical Slit FET (VeSFET) for Highly Periodic Layout and 3D Integration, W. Maly (Carnegie Mellon Univ., USA), N. Singh, Z. Chen, N. Shen, X. Li (A*STAR, SINGAPORE), A. Pfitzner, D. Kasprowicz, W. Kuźmicz (Warsaw Univ. of Techn., POLAND), Y.-W. Lin, M. Marek-Sadowska (Univ. California, USA)
    • Vertical-Slit Field-Effect Transistor (VeSFET) - Design Space Exploration and DC Model, A. Pfitzner (Warsaw Univ. of Techn., POLAND)
  4. xTCA for Instrumentation
    • AMC Vector Modulator for the LLRF System, K. Czuba, S. Bou Habib, D. Sikora (Warsaw Univ. of Techn., POLAND)
    • Automated Generation of FRU Devices Inventory Records for xTCA Devices, J. Wychowaniak, P. Perek, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • EPICS-based Visualisation and Control in DAQ Systems, P. Prędki, A. Piotrowski, M. Orlikowski, T. Kozak, G. Jabłoński, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Low Phase Noise PLL Based LO Generation Module for Femtosecond Precision RF Field Detection, Ł. Zembala, K. Czuba (Warsaw Univ. of Techn., POLAND), M. Hoffmann, F. Ludwig, H.-C. Weddig (DESY, GERMANY), M. Żukociński (Warsaw Univ. of Techn., POLAND)
    • Module Management Controller for MicroTCA-based Controller Board, P. Perek, A. Mielczarek, P. Prędki, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Performance Optimisation in Software for Data Acquisition Systems, A. Piotrowski, M. Orlikowski, T. Kozak, P. Prędki, G. Jabłoński, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • uTCA-based Controller, A. Mielczarek, D. Makowski, G. Jabłoński, A. Napieralski, P. Perek, P. Prędki (Tech. Univ. Łódź, POLAND), T. Jeżyński, F. Ludwig, H. Schlarb (DESY, GERMANY)

The following papers has been awarded:

  • Outstanding Paper Award was presented to:
    • Adjustable Trapezoidal Waveform Generator with Edge-Rounding Ability, M. Jankowski, G. Jabłoński (Tech. Univ. Łódź, POLAND)
    • A Fast and Accurate SystemC-AMS Model for PLL, K. Ma, R. Van Leuken (Tech. Univ. Delft, THE NETHERLANDS), M. Vidojkovic, J. Romme (Holst Centre, THE NETHERLANDS), S. Rampu (Decawave, IRELAND), H. Pflug, L. Huang, G. Dolmans (Holst Centre, THE NETHERLANDS)
    • An Analogue Electronic Circuits Specification Driven Testing with the Use of Time Domain Response's Features, P. Jantos, T. Golonek, J. Rutkowski (Silesian Univ. of Techn., POLAND)
    • An Open-loop Clock Generator for Fast Frequency Scaling in 65nm CMOS Technology, S. Höppner, S. Henker, H. Eisenreich, R. Schüffny (Tech. Univ. Dresden, GERMANY)
    • Considerations on Incremental Approach to Hardware Implementation of Smith-Waterman Algorithm, A. Pułka, A. Milik (Silesian Univ. of Techn., POLAND)
    • CT Images Processing as One of the Stages in Knee Joint Alloarthroplasty, P. Zarychta, J. Kawa (Silesian Univ. of Techn., POLAND)
    • DVB-CSA Encryption in Digital Hardware, P.M. Szecówka, P.W. Marucha (Wrocław Univ. of Techn., POLAND)
    • Fast Hybrid Pixel Detectors with Continuous Read in Deep Submicron and 3D Technologies, P. Maj, P. Gryboś, R. Szczygieł (AGH Univ. of Science and Techn., POLAND)
    • Improved Efficiency in the CMOS Cross-Connected Bridge Rectifier for RFID Applications, H. Rabén, J. Johansson, J. Borg (Luleå Univ. of Techn., SWEDEN)
    • Modelling of Signals Handling with Alvis, M. Szpyrka, P. Matyasik, R. Mrówka, L. Kotulski (AGH Univ. of Science and Techn., POLAND)
    • Physics-Based Modeling of Nonplanar Nanodevices (FinFETs) and Their Response to Radiation, M. Turowski, A. Raman (CFDRC, USA), W. Xiong (SEMATECH, AMD, USA)
    • Smart Gain Partitioning for Noise - Linearity Trade-Off Optimization in Multi-Standard Radio Receivers, S. Spiridon, F. Spiridon, C. Dan, M. Bodea (POLITEHNICA Univ. Bucharest, ROMANIA), F. Op't Eynde (Audax Tech. Ltd., BELGIUM)
    • Test of a Majority-based Reversible (Quantum) 4 bits Ripple-carry Adder in Adiabatic Calculation, S. Burignat, A. De Vos (Ghent Univ., BELGIUM)
    • The System Supporting the Clinical Observation of Eyeball Movements, A. Jurkowlaniec, T. Dybizbański, M. Szulc (Poznań Univ. of Techn., POLAND), S. Michalak (Poznań Univ. of Medical Sciences, POLAND), A. Figas, K. Gugała, A. Rybarczyk (Poznań Univ. of Techn., POLAND)
    • Towards a gm/Id Design Methodology for Polymer-based Organic Thin Film Transistors, F. Zanella (CSEM and EPFL, SWITZERLAND), A. von Mühlenen, Z. Szamel, G. Nisato (CSEM, SWITZERLAND), C. Enz (CSEM and EPFL, SWITZERLAND), J.-M. Sallese (EPFL, SWITZERLAND)
    • Trainer 1149: a Boundary Scan Simulation Bundle for Labs, A. Jutman (Tallinn Univ. of Techn., ESTONIA), S. Devadze, K. Shibin, V. Rosin (Testonica Lab, ESTONIA), R. Ubar (Tallinn Univ. of Techn., ESTONIA)
  • Poland Section IEEE ED Chapter Special Award was presented to:
    • Hall Effect Sensors Performance Investigation Using Three-Dimensional Simulations, M.-A. Paun (EPFL , SWITZERLAND), J.-M. Sallese, M. Kayal (EPFL, SWITZERLAND)

Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024