Automated Diagnosis of HV/LV and Floating Gate Faults in VLSI Design

Q. Zhu (International Technological Univ., USA)

This paper presents CAD methods and programs to trace the connectivity of hierarchical netlists in VLSI circuits. It detects two types of faults: HV/LV connection faults and floating gate faults. Data structures and programs are designed to process large-size circuit netlists in efficient way. Experimental results and debug GUI capability are described in this paper.